1. Field of the Invention
This invention relates to a control method for performing high speed burst operation and an apparatus thereof in memory device which can perform high speed burst Read/Write operations in response to a next generation bus clock frequency.
2. Description of the Prior Art
As dynamic random access memories(DRAMs) used in a major memory device of a computer have been developed in various types, a high speed DRAM of clock synchronous type has been usually mounted on a system requiring higher performance such as a workstation. The reason for mounting the DRAM on the system is not only to increase memory bus clock frequency, but also to increase data transmission speed.
A major standard DRAM which is widely provided in the world market is a product having a fast page mode, thus a fast page mode DRAM has been used in almost all systems from high cost products having good performance to low cost products.
However, an extended data out (EDO) mode type DRAM which is an improvement from the fast page mode DRAM of a non-synchronous type has been also used in the world market in response to continuously developing systems which require a faster operation cycle. Namely, a major advantage of the EDO mode type DRAM is to provide a faster operation cycle at the same manufacturing cost as that of the fast page mode DRAM. In a case where RAS access time tRAC is maximum 50 nsec, an operation cycle time of the high speed page mode type DRAM is minimum 35 nsec, while that of the EDO mode type is less 20 nsec.
Accordingly, a major memory device of the EDO mode type DRAM can operate a memory bus having 30-40 MHz clock signal. But, if the bus clock frequency is over 40 MHz, it is difficult to use the EDO mode type DRAM.
In order to solve this problem, a burst EDO mode DRAM which can increase the clock frequency with respect to that of the EDO mode type has been disclosed by the Micron Company. In such DRAM, in case that the RAS access time of the DRAM is 50 nsec, the operation cycle time of the burst EDO mode is 15 nsec, shorter than that of the EDO mode type. The using method of both the burst EDO mode type and the EDO mode type DRAMs are almost same, but the burst EDO mode type DRAM can be operated in response to a bus clock frequency of 40-50 MHz, which is higher than that of the EDO mode type.
On the other hand, since a bus clock signal of P6, which is a next generation microprocessor of the Intel Inc. in U.S.A., has a frequency of 66 MHz, a main memory having a data transmission speed such as 66 MHz should be used so that the microprocessor can transmit the data without a waiting time. In case that the maximum RAS access time tRAC is 50 nsec, the maximum cycle frequency is 66.7 MHz in the burst EDO mode type DRAM, while the CAS access time tCAC is increased to 10 nsec. Thus, it is difficult to match the bus clock frequency of 66 MHz.
Meanwhile, the synchronous type DRAM can be used for a 66 MHz bus clock signal, but application of the synchronous type DRAM to the main memory of a personal computer is delayed due to a higher cost of the synchronous type DRAM than that of the EDO type DRAM.
In a case of the present burst EDO type DRAM, since the burst cycle time tPC is at minimum 15 nsec and CAS access time tCAC is at maximum 10 nsec in a product whose RAS access time tRAC is 50 nsec, the maximum operation frequency is 66.7 MHz.
However, it is difficult for the burst EDO mode type DRAM to operate at the maximum frequency 66.7 MHz after the system is constructed. The major problem is in the time it takes for the /CAS signal to become the "Low Active" after outputting the data. In other word, since if the data is read at the burst cycle time tPC of 15 nsec, the tCAC becomes 10 nsec. So the time it takes for the /CAS signal to become "Low Active" after outputting the data is 5 nsec, but the time the data is assuredly maintained for only 3 nsec. Accordingly, there is a problem in a timing-design because of the skew between signals and the delay in the wiring.
Under these circumstances, the maximum operation frequency of the memory device should be over 100 MHz and the tCAC should be shortened as much as possible so that the main memory of the PC is used in accordance with a high speed operation of 75-100 MHz which are regarded as the next generation bus clock frequencies.
FIG. 1 is a timing diagram illustrating the read operation of a conventional EDO type DRAM.
With reference now to FIG. 1, in a case where a /RAS signal is "Low Active", if a row address XA is inputted and a column address YA is inputted thereof, and the /CAS signal becomes the "Low Active" after a time tRCD1 (i.e., the time at which the /CAS signal becomes the active status after the /RAS signal is activated) is passed, the data DA0 from the first column address YA to the data DA3 from the third column address YA are subsequently outputted. Specially, the first data DA0 is outputted after the time tCAC from the /CAS signal which is low-activated after a time tRCD2 (tRCD2 is the time at which the /CAS signal is toggled from a first logic high level to a logic low level after both the /RAS and /CAS signals are activated). In FIG. 1, the data DA0-DA3 and DB0-DB3 for the column address are subsequently outputted and then /WE signal becomes the "Low Active", so the burst read operation is ended. The /WE and /OE signals are inputted in a non-synchronous type with no relation to the /CAS signal. In case that a sequent burst data of more than four is read, it is okay if a new column address is inputted at every fourth /CAS falling edge after the first column address is inputted.
FIG. 2 is a block diagram illustrating a column path of a conventional burst EDO type DRAM.
With reference to FIG. 2, since a two stages pipe line structure which can adjust a column address latch 10 and datainput/output buffers 12 and 14 to the /CAS signal, a higher speed operation of a column access can be performed than that of the EDO mode type. However, the burst mode type DRAM is operated by the non-synchronous type DRAM which does not use an external clock signal, and the two stages pipe line are merely applied, thereby not shortening the time tCAC any further.
As described above, there is a problem that the conventional burst EDO mode type DRAM is operated by the non-synchronous type DRAM which does not use the external clock signal, and the time tCAC is not shortened since the 2 stages pipe line structure is applied. Accordingly, there is a problem in that the conventional burst EDO mode type DRAM does not operate at a maximum frequency of 66.7 MHz after the system is constructed completely.